The last 12 months has seen rapid takeup of fully-depleted silicon-on-insulator (FD-SOI) process technologies. With production at foundries such as GlobalFoundries and Samsung now in full swing, more and more analog designers are reaping the benefits of FD-SOI.
At Thalia we’ve been at the forefront of some of these changes, having worked on multiple customer projects that use FD-SOI technology.
So I thought that now would be a good time to take a look at some of the drivers behind this shift, and the benefits and challenges it can bring for the analog designer.
Figure 1 contrasts the structures of traditional bulk planar and SOI type transistors. The main difference is the inclusion of a buried oxide layer that isolates the channel of the transistor from the bulk silicon of the substrate. This results in a very thin, controllable channel structure, with much lower leakage currents being ‘lost’ into the device substrate than traditional alternatives.
This in turn improves two key figures of merit for the device. First, standby power consumption is dramatically reduced. Second, the threshold voltage is much more predictable and controllable – yields are improved, and power/performance tradeoffs via voltage scaling are more easily enabled.
The penalty is that FD-SOI transistors are generally not so fast. But one other feature of the technology – particularly important for mixed signal and analog designs – allows smart designers to mitigate this effect. Biasing the body structure at a different voltage to the source enables the designer to trade speed for power: a reverse bias increases the threshold voltage of the device, making it slower, but reducing leakage current; conversely, forward biasing reduces the threshold voltage, increasing the speed of the device, at the cost of power.
Thalia has worked on a number of projects that utilize SOI technologies. A recent RF front end for Bluetooth Low Energy (BLE), for example, used exactly the techniques I have outlined above. We migrated an entire subsystem design, composed of around 30 blocks (including ADCs, PLLs, mixers, amplifiers and power controllers), to a 28nm Samsung FD-SOI process.
The circuit was verified for compliance with design specifications. Design changes were implemented to ‘nudge’ the design to meet the requirements. And we made full use of the body biasing techniques I have already outlined. We used reverse body biasing to keep leakage as low as possible in parts of the circuit in which speed was not a factor; and, where speed was a key requirement, implemented forward gate biasing to increase performance.
We’re expecting increasing numbers of customers to start moving their analog and mixed signal designs to SOI technologies in the coming months and years. The process is not without its challenges: but with an intimate knowledge of the of circuit design and optimization, and of the subtleties of the processes themselves, there are substantial advantages to be reaped.