We are extremely successful efficiently migrating, refining and optimizing existing IP for new technologies and applications. Specifically, we are able to reduce the number of iterations it takes to get from our starting point – analysis of the process technology – all the way to layout migration.
However, layout migration is one step that remains very challenging and it’s worth taking a little time explaining why it remains resistant to automation.
Firstly, layout migration is never uniform: it’s almost by definition a custom design process, in fact. If you move from, say, one semiconductor platform to another or from 40 nanometre to 28 nanometre, it’s not just the names and numbers that change – the chip’s characteristics also change.
The layout needs to factor in those aspects: the way the devices are placed, the metals, the routing, how the chip is configured. But that’s not all. The way you position or place the structures on the layout is also going to have an impact on circuit characteristics. So too is the size of nodes.
Essentially then, the size of the chip is dependent on how you put together the layout – and the factors you are dealing with are not uniform.
Design simulation is also affected. Schematic-level simulations and layout simulations were once comparable. Now they are diverging – mainly because there are various elements that schematic-level models cannot factor in.
Capacitance is another issue. There are fancy equations to explain this but, put very simply, it’s about ever smaller conductor-to-conductor spacing and the knock-on effect of parasitic capacitance, which impacts the frequency ranges and the circuit characteristics. Parasitics in these ever-smaller dimensions have become a big issue.
All of which explains why full-on layout automation is so challenging: it needs to address all the problems layout design can throw up. The reality is it can’t.
But that’s no reason to abandon automation entirely. Our IP re-use platform tool – AMALIA – does not generate a complete layout factoring in all circuit characteristics, device sizes and parasitics. For the moment, that is impossible.
However, generating a base framework that compares with the base design in aspect ratio, device placement and routing of main signal nodes will assist the layout designer with a good starting point. About 20-25 per cent of the layout work should be speeded up when we reach this point. This should happen in the next 12 months.
The goal is to have something that builds a basic framework of the layout. And if you can offer that you will reduce the amount of time a layout designer would have to spend then putting together the layout.
Thus our aim is targeted automation – and that is achievable. What isn’t achievable – and may never be – is an all-singing, all-dancing layout automation tool. If someone offers you that, be very, very wary.